jks

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jks
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  • v1.161: FSK/RTTY extension

    Looks like I forgot to enable it. It will be available in v1.161 later today..

    WA2ZKDKA7U
  • Software control of fan in enclosure?

    No software mechanism. The 3.3V on the Grove connector of the BBG the fan plugs into is a fixed voltage.

    You could buy one of the short Grove cables from Seeed. Connect to the BBG and run the other end out the slot where the antenna connectors are. Disconnect the fan from the BBG and run the cable out the slot also. Cut the two Grove connectors off the cables and wire up appropriately to a little switch.

    james
  • NAVTEX Idea [DX log mode]

    That a really good idea. Added to the list.

    KA7UWA2ZKD
  • Ethernet interface unreliable - very serious problem [fixed with better power supply cable]

    Get a new BBG from Seeed. They should never have been asking customers to be removing components. That is completely unprofessional behavior and I will be speaking to them about that.

    WA2ZKD
  • Audio-underruns when using kiwisdr.local on WIndows 10 Pro - a solution

    Yes, I had another customer report this same situation a few days ago. I find it completely impossible to understand why this would make any difference to the quality of the connection.

    No, scratch that. It's Windows. It's Microsoft. I should completely expect a nonsensical situation like this. It goes right along with the hundreds of millions of person-hours Microsoft has caused humanity to waste dealing with their incompetence. Just yesterday I upgraded an old laptop to the newest release of Windows 10. The WiFi stopped working. I spent hours trying to figure it out. In the end the answer was that the manufacturer, hp, had used an internal WiFi card whose manufacturer was no longer updating the drivers. But there was no warning from anyone that the update would kill the WiFi. Hp says there is no solution except to buy a different PCIe WiFI card. Can you imagine that kind of response from a manufacturer?

    Apologies. Someone's morning coffee obviously hasn't taken effect yet. lol

    fvink
  • NAVTEX Idea [DX log mode]

    That a really good idea. Added to the list.

    KA7UWA2ZKD
  • Alternative Kiwi map with status and day/night overlay

    New from pryiom.org is rx.linkfanel.net, an alternative to sdr.hu/map that features color coded Kiwi status and a day/night map overlay.
    Thanks Pierre!

    KA7USergeWA2ZKDrz3dvp
  • http://ve3sun.com/KiwiSDR/index.php

    Be sure to send a reception report to www.rnzi.com as it says in the DRM info window. I'm sure a lot of these broadcasters sending DRM wonder if they are wasting their time doing so.

    KA7U
  • Is it possible to transform kiwi sdr on Xilinx Zynq FPGA a single chip solution [for GPS only]

    Hi,

    When you get acquisitions do the PRNs (sats) agree with those known to be visible in the sky? (i.e. as reported by another working GPS receiver). I guess you pretty much said yes. If acquisition is working then you know the constants FC, FS and FS_I must be set to the correct values for the NT1065. Max SNR values of 50 are fine (will depend on your antenna). I don't think the increased sampling bandwidth will matter much to the SNR because it is derived from the normalized output of the acquisition FFT. But I am no expert about that.

    If the RSSI during the tracking phase is never over 300 then the tracking loop is probably never locking. Have you tried tracking using the SE4150? Does it ever lock? A lot of things have to work correctly for the tracking loop to lock.

    There is some Verilog Andrew has called logger.v It is a buffer for storing IQ samples from the tracking loop. There is Verilog in gps.v to attach logger.v to the PUT_LOG, GET_LOG and LOG_RST commands sent by ecpu code. But there is no ecpu code currently to send these commands. But it would not be difficult to add. You would just be using PUT_LOG to save the I & Q values from the tracking loop to the buffer. And then implement a command sent from the host (Beagle) side that uses GET_LOG to upload the IQ values through the SPI. If the loop is locked you'll get a stable IQ display pattern like what is shown on Andrew's site. Look for the graph that has the heading "(ii) Lock". 

    When you are decimating 4:1 in the FPGA from the 65 MHz sample rate of the NT1065 to 16.354 MHz are you doing decimation properly by first filtering the signal bandwidth before downsampling by 4? If you don't filter then you will be aliasing signal and/or noise into the decimated passband and this is perhaps why tracking doesn't lock.

    Navnath123
  • Grove Project

    I have another version of that table that covers all the Beagle P8/P9 pins if the Grove UART pins are not on there.
    There is a similar one in the BeagleBone Black system reference manual (SRM): System Reference Manual

    WA2ZKD