jks
About
- Username
- jks
- Joined
- Visits
- 32,524
- Last Active
- Roles
- Member, Administrator, Moderator
- Points
- 344
Reactions
-
Is it possible to transform kiwi sdr on Xilinx Zynq FPGA a single chip solution [for GPS only]
Hi. Yes, to use real-time GPS data from the Kiwi GPS front-end chip you will need to run the code on the embedded processor on the FPGA. This is the code (sdgps/asm/gps.asm) that runs in the little FPGA embedded processor (sdgps/a_ise/gps_iq15_1/cpu.v) that also has a C-code simulation (sdgps/cpu/cpu.c).This is because for real-time GPS data this code needs to run PLL loop filter code at 1 kHz.See Andrew's description here: http://www.aholme.co.uk/GPS/Main.htmI don't think my simulation code is fast enough to do this in real-time. Anyway, the simulation code only simulates both the GPS FPGA logic (e.g. sdgps/a_ise/gps_iq15_1/demod.v) and the embedded processor together. It does not know how to work with the GPS logic running in the actual FPGA but the embedded processor simulated. But this embedded processor is quite simple and shouldn't be much of a problem to get working on the Zynq.There is another problem to consider. My old "sdgps" project that you have running is targeted for a Spartan-6. But also for the Xilinx ISE toolchain. I believe Zynq requires the newer Vivado toolchain. So you will have to make some adjustment, e.g. instead of a .ucf format file for the FPGA pin mappings you will need a .xcf format file. And the definitions for the required Xilinx IP blocks is a little different. The GPS part of the newer KiwiSDR project targets the Artix-7 which of course requires Vivado. So you will find a .xcf file there and the Vivado-compatible IP block definitions.After this is working there is the question of moving the C/C++ code off the Beagle into the Arm processor of the Zynq. But that is a separate consideration.And now for something new: The "sdgps" project just outputs to the terminal as you know. And the GPS in the KiwiSDR project has this nice web interface as part of the admin page. What I've been working on the last few days is a version of the KiwiSDR project that has most of the "SDR" code removed. This will leave just the GPS code. There will be fewer files, it will compile much faster and be much easier to understand. The KiwiSDR project is currently at https://github.com/jks-prv/Beagle_SDR_GPS so I will make a new project called https://github.com/jks-prv/Beagle_GPS in a few days. I'm not sure if this will help you for using the Zedboard but I've had several requests for a version of the Kiwi for people who just want to do GPS development / experimentation and don't care about SDR. -
DRM demod? [yes, external app Dream now working!]
For Mac OS X I couldn't get the FAAD2 codec I downloaded to be recognized by Dream 2.1.1 (the latest version). But downloading the older Dream 1.11 from Download Dream 1.11 application (i386) worked immediately (has the codec bundled). Select your VAC as the input device and set the channel to "I/Q positive zero".I need to do a little more cleanup before releasing v1.139 with the new IQ mode. The changes are on the Kiwi at kiwisdr.sk3w.se:8073 if anyone wants to try it. I'd like to know if the Windows version of Dream works. -
Is it possible to transform kiwi sdr on Xilinx Zynq FPGA a single chip solution [for GPS only]
Hi. Yes, what you want to do is possible. But it is a lot of work. It is maybe easier to start with the GPS code that does not have the Kiwi SDR code parts: http://www.jks.com/sdgps/sdgps.html This code just runs a program on the Beagle that prints messages with no web interface and no complications of all the Kiwi SDR code.1) How are you wiring the Beagle SPI to the Zedboard? Are you using the same SPI pins as go from Beagle to Kiwi FPGA? This is tricky because those same pins are used to download/program the Kiwi FPGA. Did you somehow electrically isolate the Kiwi FPGA from those SPI pins? Otherwise you have to depend on the Kiwi FPGA power-up state to leave those pins in high-impedance mode. It is possible this is okay even if you did not isolate the pins.2) Did you disable the code in the Kiwi server that programs the Kiwi FPGA?3) Admin page not connecting: In the browser open the "javascript console window" and look for error messages. Each browser has a different way of doing this. On Firefox from the top menu bar select: Tools > Web Developer > Web Console and then make sure the Console tab is selected.4) Do you get any error messages on the Beagle console when you run the Kiwi server? -
CPU load is inversely proportional to the number of receivers?
It's not that simple. The Kiwi is a very complicated realtime system. There is a careful balance of resources to minimize the cost of the device while maximizing the number of supported channels. This means there is sometimes a tradeoff between FPGA resources and Beagle cpu cycles.What you're seeing at first is the GPS acquisition process (very Beagle FFT intensive) being paused when the first connection occurs. And with no connections the audio data pump between FPGA and Beagle is shut off causing a big reduction in system time due to fewer SPI transfers.The %load number you show looks like user time only. You have to consider system (kernel) time as well. I see numbers like this:#recv %user %sys %idle %busy0 96 3 0 1001 60 18 20 802 41 23 33 673 41 22 33 674 46 22 30 70This is about optimal. For no connections you want to spend all available cycles acquiring new GPS sats for maintaining ADC clock calibration. When there are corrections you want to have some cycles leftover for the portion of extension code that runs on the Beagle. -
IBP Button to track beacons