jks

Switch off the other devices until you find the culprit. Try filtering the mains input to your Kiwi linear power supply and perhaps Ethernet and antenna feed line.

Since you're using DUC on no-ip.com, on the sdr.hu tab selection menu at bottom left, do you have "DUC Domain" selected? And does it show "the_host_name_you_setup.ddns.net"?

On the network tab what yes/no answers do you get when you push the "check port open" button?

I used the wrong command to restart the server after making a change and now I can't get back in.. Thanks.

The ADC clock counting occurs before the DDS and is unaffected by any tuning compensation. You're correct, the "slightly off" sample rate derived from the division of the ADC clock is not corrected. But it doesn't matter. You just want to fix the downstream effects of the sample rate being slightly off. Namely getting the waterfall to look "on frequency" and the audio to produce the exactly correct tones. If you can determine what the exact, slightly off, constantly changing sample rate is using the GPS then this should be similar to having used a very expensive TCXO/VCTCXO with no GPS involved at all. Fixing the tuning completely compensates for the sample rate being off.

The 48-bit counter in the FPGA, clocked by the ADC clock and sampled by the GPS, is very similar to a traditional frequency counter. If the gate time of the counter is known to be accurate then the ratio of the counter to the gate time gives you the frequency: ADC_clk (Hz) = ADC_count / GPS_gate_time, where Hz is "counts" per second and GPS_gate_time is the difference between two GPS time samples measured in seconds. Another way:

ADC_clk (counts)   ADC_count (counts)             1

---------------- = ------------------- X -------------------

        (sec)                            GPS_gate_time (sec)

The software GPS in the Kiwi doesn't even have a 1 PPS. It produces a new GPS position/time solution every 4 seconds or so and GPS_time is simply the difference between two successive solutions. Since both solutions are accurate to roughly a microsecond the "gate time" is accurately known. There is one more thing required. In the FPGA the ADC clock counter is sampled simultaneously when the GPS hardware that determines a solution is sampled. So the sampling is synchronized.