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Is it possible to transform kiwi sdr on Xilinx Zynq FPGA a single chip solution [for GPS only]

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Comments

  • jackobianjackobian
    Sir. in search.cpp i found that lookup table does not repeat periodically.  it should be something like 0,1,2,3.0,1,2,3.....etc, but in my case it is random. does that affect my design?
  • jksjks
    edited April 2018
    Which lookup table is that? And also which version of the software. The one from the "sdgps" project?

    Do you mean this?
    static const SATELLITE Sats[NUM_SATS] = {

    The "for" loop in SearchTask() is supposed to try all entries from Sats[] sequentially. You don't have PRN_LIST defined do you? In gps.h, if PRN_LIST is defined then only satellites from the PRN_VISIBLE list will be searched for. So double-check that.

  • jackobianjackobian
    No. i mean look up table for sin ,cos function [1,1,0,0]. then 4*FC/Fs?
  • jksjks
    The code is correct. Depending on your specific values of FC and FS you may see indexing into the lo_sin/cos arrays that appears random. Specifically, if the number lo_rate = 4*FC/FS is fractional then the value of lo_phase will not be sequential. On the Kiwi, using the SE4150L, with FC=4092000, FS=16368000 then lo_rate = 1.0 But if you're using FC=5691000, FS=10000000 then lo_rate = 2.2764 and lo_phase will have odd values as lo_rate is added to it modulo 4, i.e. the code:
    lo_phase += lo_rate;
    lo_phase -= 4*(lo_phase >= 4);

    I'm using FC=5691000 because I'm assuming you're sampling the gp2015 IF=4309000 with a 10 MHz FS. So FC=FS-IF.
    But now I realize I'm confused about something. On the Kiwi the SE4150L uses IF=4.092 MHz but FC is also set to 4.092MHz and not 12.276=16.368-4.092 (FC=FS-IF). But in Andrew's design IF=22.6, FS=10.0 and he does use FC=FS-IF (actually IF-FS since FS is under sampling the higher frequency IF) and has FC=2.6 MHz. So that's different.

    What happens if you set your FC to 4.309? (or 5.691 if you're already using 4.309)

  • jackobianjackobian
    Sir, I have test 5.691 and 4.309. But also SNR<15
  • jackobianjackobian
    Sir, In fact what i did and trying to do is this:
    1- I have andrew source code as every one
    2- i build the whole circuit of andrew, and it works very well with me, i receive signal from sats, and get my position.
    3- i want to use gp2015 instead of andrew's one. as if you did with  SE4150L .
    4-until now i chanfe Fc to 5,691 and to 4.309 with Fs=10MHz, but i got nothing
    5- i do not know where the problem is
    6- rf signal is very good.

  • soumyalpsoumyalp
    Dear all,
    With reference to the discussions on " GPS on Xilinx Zynq FPGA a single chip solution", we are able to port the sdgps project in to Zynq Soc and run it without any errors. Since we want to maintain minimal changes in the SDGPS project, we are using same SPI as the interface between FPGA and Processor(ie, PS to/from PL). After running the GPS.bin there is no "FPGA not Responding", and able to see the Empty output on the screen(only PRN and SNR are incrementing and other fields are EMPTY ). we are doubting SPI chip selects. Is it possible to give clarity on CS0 and CS1. Our understanding on CS are, CS0 is used to load .bit and .bin file to FPGA and CS1 is used for message exchange, Are we missing somthing?
    Current Issue :
    1. While printing the (Getsample Cmd)sample data received at processor from FPGA, Only first 11bytes are non zeros, others were filled with zeros. same we checked with Beaglebone + kiwiSDR setup and we noticed datas were present in all bytes.

    Regards,
    Soumya.
    image

    Attachments:
    https://forum.kiwisdr.com/uploads/Uploader/17/d1a4ccf6dfab7e1ef09151b819fc9d.png
  • jksjks
    CS0 is asserted low for every SPI transfer. On the Beagle it is part of the SPI hardware. CS1 is a software-driven chip select. When CS1 remains de-asserted (i.e. high) during CS0 asserted the SPI transfer is being used to load the memory of the e_cpu in the FPGA. When CS1 is asserted (low) along with CS0 the SPI transfer is sending a command to be read by code running in the e_cpu.

    To debug problems with data transfers send some test patterns. Do this by modifying the code running on the e_cpu to send a data pattern instead of GPS data. Change the code in gps.asm UploadSamples to send data. Replace the part that says "wrEvt GET_SAMPLES" to "push 0x1234" and then look for this data in your print of the GPS sample data.

    If that is working then there is a problem in the data you are sending from the GPS front-end chip to the FPGA or a problem with the sample buffer in the FPGA (the buffer that "wrEvt GET_SAMPLES" is reading from.
  • soumyalpsoumyalp
    edited May 2018
    Hi,
    we have changed "wrEvt GET_SAMPLES" to "push 0x1234" in gps.asm file, (received are 0x12 and 0x34 in the screen shot)
  • jksjks
    Okay. What about removing the GPS front-end chip data line from the FPGA and then just pulling that FPGA pin high or low (through a 10K resistor or something) to see if the data follows the pin input? Put the "wrEvt GET_SAMPLES" back and be sure the GPS clock signal is still present.
  • jackobianjackobian
    Sir, In fact what i did and trying to do is this:
    1- I have andrew source code as every one
    2- i build the whole circuit of andrew, and it works very well with me, i receive signal from sats, and get my position.
    3- i want to use gp2015 instead of andrew's one. as if you did with SE4150L .
    4-until now i chanfe Fc to 5,691 and to 4.309 with Fs=10MHz, but i got nothing
    5- i do not know where the problem is
    6- rf signal is very good.
This discussion has been closed.