DDC on FPGA

train04train04
edited February 2018 in Problems Now Fixed
HII,
 I read full document of SDR design , in this SDR design you are using IQ Mixer, DDS, CIC and FIFO. 
But we  know that in Vivado There is DDC/DUC IP core is available , so why we are not using this core directly instead of using these complicated things.
please reply.

mai ID -- shubhamgwl04@gmail.com

Comments

  • jksjks
    Hi. That is an excellent question.

    If you look carefully at the free version of the DUC/DDC compiler provided with Vivado you'll see that it is not general purpose. It is targeted to the cell phone industry (LTE/CDMA) and does not have the bit widths, clock rates and decimation factors needed by the Kiwi.

    The Kiwi does take advantage of some Vivado IP blocks, like the DDS compiler. And it makes very heavy use of the Artix DSP blocks to save FPGA fabric gates. We also wanted to have a design fully independent of any FPGA manufacturer's architecture in case we need to change devices in the future. It was also a learning experience for us to implement everything from first principles.

    KA7Utrain04
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