OV Worries

WA2ZKDWA2ZKD
edited December 2017 in Problems and Issues
How much OV flickering is acceptable? How much activity can occur before weak signals are affected?

Comments

  • jksjks
    I've explained this somewhere before (it really needs to be a FAQ so people can find it).

    The current FPGA logic just records an OV event if a single overflow is reported by the ADC. This is nonsense of course. You'll get overflows during normal operation as all those sine wave peaks from strong HF signals just happen to sum up during one ADC sample. That in itself is not a bad thing. You won't hear distortion because of it. Some sort of averaging of the ADC overflow output needs to occur and only when a threshold is exceeded should an OV event occur. 

    And that's really your question: what should the threshold for ADC overflows be before an error indication is given? You could even imagine a a couple of different threshold being shown, done e.g. with colors.

    WA2ZKD
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