Repairing KiwiSDR receiver after thunderstorm.
Hello. KiwiSDR stopped working after the thunderstorm. The power supply goes into protection. There is a short circuit on the KiwiSDR power connector.
The BeagleBone board also stopped working. Separately from the KiwiSDR, the BeagleBone shows no signs of life and the TPS65217C chip is very hot.
The problem was not only in the failed transformer T301. The 5V power line had a resistance per mass of 5 ohms.
All linear stabilizers are out of order. Three pieces LP5907 and LMR10530Y. Moreover, the LMR10530Y was pierced through. That is, the 5V input was connected to the 1V output.
For further diagnostics, the stabilizers were replaced with similar ones.
KiwiSDR is working, but additional testing is required.
I made a short video of this repair.
Comments
I have long wanted to try replacing the SMPS LMR10530Y with a linear one. Since this SMPS is out of order and I do not have the opportunity to buy an original or an analogue, I still used a linear one based on the uPC7706. Measured current consumption of FPGA 1.0V 170-180mA. It gets quite hot. About 80-90 degrees Celsius, even considering that I used the ethernet connector for cooling. But long-term tests showed stable operation.
I don't understand this at all. If you really put 5V on the FPGA's 1V power inputs it should be DEAD. 5V would have instantly punched through all of those 28 nm gate structures!
The LMR10530 had zero resistance between the power input and output after a thunderstorm. However, it also had a resistance of 5 Ohms to ground at the input and output. Perhaps this saved the FPGA.
Well, that's amazing. But I learn something new about this project almost every week. Thanks for taking the time to document this.
The LMR10530 pulse stabilizer cannot be purchased. I've also been looking for analogues for a very long time, at least a little similar in pinout. It ended in failure. ChatGPT and DeepSeec couldn't help me either. I ordered several pieces of TLV62569 pulse stabilizers. They differ from the LMR10530 in the frequency of the converter (1.5 MHz instead of the required 3.0 MHz) as well as the reference voltage. And of course the pinout. I will try to install these stabilizers soon. I hope it will work.
Really? From TI's online store. 497,630 in stock.
If you keep in mind which country I'm in, then I don't have any available options for buying these chips )) Or price is so high, so i can not let myself to by it.
Alsow, look at min quanity of order ))
Let me ask our manufacturer if they can take some off their reel so we can send to you. Please send your postal address (not DHL parcel address) to support@kiwisdr.com
John, thank you so much for your suggestion! But I want to try to repair the KiwiSRR on my own, using cheap and affordable components. As you can see, I have installed a linear stabilizer to power the FPGA 1.0V. It has been working fine for several months now.
Today I installed the TLV62569DBVR pulse stabilizer instead of the failed LMR10530Y. Their reference voltage is the same, so there is no need to change the voltage resistive divider.
I used an oscilloscope to check the shape of the pulses at the output of the TLV62596 SW chip and was surprised. The generation frequency is unstable and varies rapidly from about 600 kHz to 1500 kHz. I consulted the Texas Instruments documentation and, according to the recommendations, replaced the inductor with 2.2 uH and the output capacitor with 2x22 uF. The generation frequency became stable at 614 kHz, which surprised me even more! The TLV62596 generation frequency should be 1500 kHz. In addition, it caused severe interference on the KiwiSDR waterfall at 614 kHz. I consulted the documentation again and found that the generation frequency depends on the load current. This is fully consistent with the document. With an FPGA current consumption of about 180 mA, the generation frequency is 600 kHz.
I had to increase the load by adding a 2.2 ohm resistor. The generation frequency is now stable and is approximately 1500 kHz.
This work is nothing short of amazing. Great job. Also, thats for measuring the current of the FPGA 1V0 rail. I had always wondered about that. I would not have guessed such a low value. It's true that none of the FPGA logic switches above the ADC clock (66.7 MHz) which is relatively tame compared to what the FPGA is capable of (300-400 MHz).
Thank you, John! I was very very interested in investigating this. By the way, while the Kiwi server is not launched, the FPGA consumes about 60 mA. And by the way again ... I was offered to leave this Kiwisdr for myself. And I made a case for two recrviers ))