LTC2254 105 Msps ADC instead of the LTC2248 65 Msps ADC

edited July 2017 in Problems and Issues


  • Is it possible to offer a hardware version of KiwiSDR that offers the LTC2254 105 Msps ADC instead of the LTC2248 65 Msps ADC.
    They are drop in pin for pin replacements as far as my reading of the datasheets tells me.
    If that ADC is used then that opens the door to a 98.304 MHz external clock reference (which then gives integer maths relationship with a 48 KHZ output sample rate) and it is also is incidentally an integer divide rate for the 12.288 MHz used by USB standard.
    The 98.304 MHz clock also enhances performance of the receiver up to 30 MHz as the input lowpass filter has a much easier job removing alias frequencies. 66 MHz ADC clock makes that a hard ask and limits the receivers performance above 20 MHz, due to aliases
    The price difference between the LTC2248 and the LTC2254 is around $20 USD and the 105 Msps ADC allows software and FPGA enhancements, but the LTC2254 would still work with the software and FPGA development as it currently stands, using the 66 MHz reference.
    A 98.304 MHz reference does require modifications within the software but it does offer significant performance enhancements going forward, and is a way to solve the skew problems experienced when demodulating HF Fax signals.
    Comments please
  • jksjks
    edited July 2017
    I didn't mention it on the forum, but the FAX skew/slant problem was fixed in the v1.100 release ( It was just a software bug. The audio sample rate not being a rational number doesn't matter. It just has to be accounted for, which it wasn't.

    As I've mentioned many times the Kiwi (this version at least) is a very careful balance of design choices, including component selection, to meet a set of design goals. One of which is a relatively low retail price while still having a 14-bit ADC and FPGA. Another is that it's a "shortwave receiver" class of device. Not a ham contest-grade receiver. So the high end of HF suffers a bit in performance in signal environments where aliasing is going to be a problem. It receives fine on 10m (e.g. go listen to But you have to deal with the limitations. Just like with the dynamic range limitations of a 14-bit ADC.

    Component pricing is a complicated topic. There is pricing from distributors and then there is often substantial discount you can get by going to "inside sales" when your purchase quantity is sufficient. I don't know exactly what Seeed is paying for the current ADC (LTC2248). The last Q1k quote I had from LTC inside sales was in the low US$20 range. This kind of pricing is essential to meet the US$199/$299 retail price targets.

    Some distributor pricing via for various ADCs @ Q1k:
    LTC2248 14b/65M $27.69
    LTC2249 14b/80M $29.64 +$1.95
    LTC2254 14b/105M $58.57 +$30.88
    LTC2205 16b/65M $50.97
    LTC2206 16b/80M $56.85 +$5.88
    LTC2207 16b/105M $66.68 +$15.71

    1) At the time the Kiwi was designed there was a much greater price difference between the 65M and 80M versions of the 14b part.
    2) Note the $31 difference between the 65M and 105M 14b part, not "about $20". But this is only a distributor pricing comparison.

  • Notwithstanding the above, should there be a "Kiwi v2"? Maybe. I think most would say no effort should be put into that until most of the current software bugs & enhancements are addressed.

    Your idea about offering the current hardware with an upgraded ADC + clock is actually a good one. One question is whether that should also be offered with other enhancements (front-end improvements, etc.) All kinds of other ideas have been floated. Some of which are really interesting.

  • I think it might be good to build a dedicated Kiwi with as much FPGA or more and a better ADC but as a transceiver for single HF bands - 200kHz for 160, 50kHz for 30m 100kHz for 17 might all be do-able
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