ADC Clock Frequency Correction via GPS Timing
I have been reading the KiwiSDR Design Review document. I'm trying to understand the system-wide clocking and timing of the system, and in particular section 6.4.6 "ADC Clock Frequency Correction Via GPS Timing" of the document.
As I understand it, the FPGAs input ADC samples and the IQ data on both audio and waterfall baseband datapaths are clocked by the 66.6667MHz oscillator, The datapaths may be slow or fast since the oscillator frequency varies over temperature. According to the document KiwiSDR corrects this using the GPS timestamps which emerge in software on the BB. GPS timestamps are compared with a software count of received samples (between successive timestamps) and used to vary the DDS frequency. Now, I can understand that this will deliver a correctly tuned DDS output. But this does NOT change the sample rate, so the sample count wont change (for a given inter-timestamp period)!
Can anyone explain the flaw in my thinking?
vk6hsr (MM in the UK)